A system receives as input a stream of data symbols which can take values from the set {a,b,c,d}. Assume that the symbols arrive on a 2-bit input pin IN[1:0], and a,b,c,d are represented as 00, 01, 10, and 11 respectively.

The system looks at blocks of 32 input data symbols and finds the most popular symbol (i.e. the symbol that occurred the highest number of times) in each block. At the first clock edge after a block of 32 input data symbols is received, the system outputs on pin Z the identity (i.e. a or b or c or d) of the most popular input data symbol in the block, and on pin F it outputs an unsigned binary integer that is one less than the frequency (i.e. frequency-1) of the most popular symbol. Clearly Z, like IN, will be a 2-bit binary signal. Since the maximum possible value of F is 31, F would need to be a 5 bit signal (i.e. F[4:0]).

For example, if in the first 32 input symbol the most common symbol was c and occurred 20 times, then the output in the 33rd clock cycle would be Z=c (i.e. Z[1:0]=10), and F=19. Then if in the block of next 32 input data symbols (i.e. symbols 33 through 64) the most common symbol was a and occurred 16 times, then the output in the 65th clock cycle would be Z=a (i.e. Z[1:0]=00), and F=15. And so on. In other clock cycles we donât care what the outputs are.

Design a FSM (i.e. a sequential circuit partitioned into a datapath and a control FSM, as we studied in the lectures) to realize this system, showing clearly.

State diagram of the FSM

State table of the FSM

Block diagram schematic of the datapath

Implementation schematic of the FSM with one-hot coding of the states in Logisim

Your design may use any standard combinational modules (simple gates, mux, demux, encoder, decoder, arithmetic functions etc.) or standard sequential modules (flip-flop, registers, counters etc.) that you are familiar with from Lectures and Logisim.

You must label inputs and outputs of any…

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